The disclosed invention relates to semiconductor memories and more particularly to the architecture of such memories. Basically, all semiconductor memories include storage cells and sense amplifiers. Storage cells are utilized to store charge which is representative of digital information. Thousands of these cells are fabricated on a single semiconductor chip. Sense amplifiers are utilized to selectively sense and amplify the charge in the cells to binary voltage levels.
Typically, the thousands of cells within the memory are fabricated in rectangular arrays. Word lines run through the array in one direction and operate to select columns of the cells. Bit lines run through the array perpendicular to the word lines and operate to receive charge from the selected column of cells and transport it to the sense amplifiers for amplification.
Over the past several years, the tendency has been to package as many of the cells into the array as possible. In general, this is accomplished by decreasing the size of each individual cell. As a result, however, the charge storage capacitor of each individual cell is decreased in size. This in turn reduces the amount of charge which can be stored in each cell and makes charge sensing difficult.
Further, each of the bit lines which connect to the cells also has an inherent capacitance. In modern high density memories, this bit line capacitance is substantially greater than the capacitance of each of the cells within the memory. Thus, as the ratio of storage cell capacitance to bit line capacitance decreases, the task of sensing the charge within the selected cells becomes even more difficult. Accordingly, it is desirable to have an architecture for a semiconductor memory which simultaneously provides for a small storage cell and a large storage cell capacitance to bit line capacitance ratio.
In the prior art, each bit line in the memory array has one sense amplifier connected thereto. Accordingly, as the size of each of the cells is decreased (in order to package more cells into the array), the size of the sense amplifier must also necessarily decrease (in order to maintain a symmetrical physical layout). Eventually, however, a point is reached where the size of the sense amplifier can no longer be decreased or it will not be able to detect charge in the cells. At this point, the minimal size of the sense amplifier prevents the size of the memory cells from being further reduced. It is therefore desirable to provide a memory architecture where the sense amplifier size does not limit the cell size within the array.
Also in the prior art, the memories included two arrays of cells with a bit line decoder alongside each array. These decoders operated in conjunction with the bit lines of the respective arrays to write information into the cells. In particular, during a write operation, the bit lines connected to one decoder acted as set leads, while the bit lines connected to the other decoder acted as reset leads. Although much of the two sets of decoding logic was redundant, they were both required since the set leads and reset leads were not available on any side of one array. Accordingly, it is desirable to provide a memory having bit lines which operate as set and reset leads during a write operation which are available on a single side of one array.
It is therefore one object of the invention to provide a semiconductor memory having an improved architecture.
Another object of the invention is to provide a memory having an improved storage capacitance to bit line capacitance ratio.
Another object of the invention is to provide a memory having storage cells which are not limited in size by the minimal dimensions of the sense amplifiers connected thereto.
Another object of the invention is to provide a memory having bit lines which operate as set and reset leads during a write cycle which are available on a single side of the array.
Still another object of the invention is to provide a memory having sense amplifiers for selectively sensing charge on four bit lines.